1. Field of the Invention
The present subject matter relates to routing connections in an integrated circuit. More specifically, it relates to prioritizing nets before routing the integrated circuit.
2. Description of Related Art
An integrated circuit (IC) has a large number of electronic components that are created by forming layers of different materials and of different geometric shapes on various regions of a semiconductor. The design process for an IC, called the physical design process, transforms a circuit description into a geometric description called a layout.
Engineers often use electronic design automation (EDA) software tools to assist in the design process. A top-down design methodology is commonly employed using hardware description languages (HDLs), such as Verilog or VHDL for example, by which the engineer creates an integrated circuit by hierarchically defining functional components of the circuit, and then breaking down each component into smaller and smaller components.
The components of an integrated circuit are initially defined by their functional operations and relevant inputs and outputs. From the HDL or other high level description, the actual logic cell implementation is often determined by a logic synthesis tool, which converts the functional description of the circuit into a specific circuit implementation. The logic cells are then “placed” by giving them specific coordinate locations in the circuit layout, and “routed” by wiring or connecting logic cells together according to the designer's circuit definitions. The placement and routing software routines generally accept as their input a cell library and a netlist that has been generated by the logic synthesis process. This netlist, or list of nets, identifies the specific logic cell instances from the cell library, and describes the specific cell-to-cell connectivity.